1. Field of the Invention
The present invention relates to a capacitor structure, and more particularly, to a capacitor structure having high performance and high yield.
2. Description of the Prior Art
In semiconductor integrated circuits (ICs), a semiconductor capacitor may be implemented to provide a capacitive component within the design of a semiconductor integrated device. The applications for these capacitors can include mixed signal (analog/digital) devices, RF (radio frequency) devices, and even decoupling capacitors for the filtering of high frequency signals and improved noise immunization.
One type of semiconductor capacitor structure, called the metal-oxide-metal (MOM) capacitor structure, is commonly used in silicon based semiconductor integrated circuits for its versatility and consistency in reproduction in semiconductor processing. Basically, an MOM capacitor structure includes two parallel electrode plates and an insulator disposed between the electrode plates. With reference to FIG. 1, FIG. 1 is a schematic diagram of a flat plate capacitor structure 10 according to the related art. As shown in FIG. 1, the flat plate capacitor structure 10 includes a substrate 12, a first electrode plate 14 disposed on the substrate 12, a capacitor dielectric layer 16 disposed on the first electrode plate 14, and a second electrode plate 18 disposed on the capacitor dielectric layer 16.
The capacitance of a capacitor structure can be expressed as Eq (1):C≈∈A/d  Eq (1)Where                C denotes the capacitance;        ∈ denotes the dielectric constant of the capacitor dielectric layer;        d denotes the thickness of the capacitor dielectric layer; and        A denotes the overlapping area of the first and second electrode plates.        
The capacitance of the flat plate capacitor structure 10 is mainly determined by the dielectric constant of the capacitor dielectric layer 16, the thickness of the capacitor dielectric layer 16, and the overlapping area of the first electrode 14 and the second electrode plate 18. In other words, in order to improve the capacitance, these three factors need to be changed.
Since the dielectric layer 16 has to be compatible with the material of the first electrode plate 14 and the second electrode plate 18, there is not much room to improve the capacitance by tuning the dielectric. In addition, an excess thinness of the capacitor dielectric layer 16 may lead to a low breakdown voltage problem. Thus, increasing the overlapping area of the first electrode plate 14 and the second electrode plate 18 is preferred. However, since the first electrode plate 14, the capacitor dielectric layer 16, and the second electrode plate 18 are stacked up vertically, the overlapping area of the first electrode plate and second electrode plate per unit volume of the flat plate capacitor structure 10 is limited. In order to increase the capacitance by means of increasing the overlapping area, the first electrode plate 14 and the second electrode plate 18 should be formed with a large area. Therefore, the integration of integrated circuits is greatly reduced by the prior art flat plate capacitor structure 10.